- 도입완료
VIP(Verification IP)
고속 인터페이스 IP 검증 솔루션
- 담당자 메모
- Cadence 사의 VIP(Verification IP)는 IP, SoC, 시스템 수준 검증을 위한 고신뢰 시뮬레이션 모델로 글로벌 반도체 기업들의 SoC 검증 환경에서 지속적으로 채택된 솔루션입니다.
PureView 기반 자동 구성과 TripleCheck IP Validator를 통해 컴플라이언스와 커버리지를 보장하며, Xcelium, Palladium, 타사 시뮬레이터에서도 안정적으로 작동하여 전체 검증 과정을 가속화합니다.
Features
- Compliance with PCIe and AMBA, Ethernet with support of critical erratas
- Verifies Root Complex, EndPoint, PHY, and Switch designs for all native widths and downgraded widths
- Comprehensive protocol checks with 3,300+ built-in checks/assertions
- Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation
- Static and dynamic setting for configuration variables available
- Root Complex, End Point, Switch, PHY DUT, Redriver 지원 가능
- Serial (NRZ, PAM4) and PIPE 6.2 (Serdes Architecture and Original Architecture)
- Supports all PCIe speeds: 2.5GT/s, 5.0GT/s, 8.0GT/s, 16GT/s, 32.0GT/s, 64GT/s
- FullVision 3.0 – new and improved high-performance debug engine
- Configurable link width support x1, x2, x4, x8, x12, x16
- Full support for up and down configuration
- Verifies Root Complex, EndPoint, PHY, and Switch designs for all native widths and downgraded widths
- Comprehensive protocol checks with 3,300+ built-in checks/assertions
- Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation
- Static and dynamic setting for configuration variables available
- Root Complex, End Point, Switch, PHY DUT, Redriver 지원 가능
- Serial (NRZ, PAM4) and PIPE 6.2 (Serdes Architecture and Original Architecture)
- Supports all PCIe speeds: 2.5GT/s, 5.0GT/s, 8.0GT/s, 16GT/s, 32.0GT/s, 64GT/s
- FullVision 3.0 – new and improved high-performance debug engine
- Configurable link width support x1, x2, x4, x8, x12, x16
- Full support for up and down configuration
