- 도입완료
AVIP(Accelerated VIP)
고속 인터페이스 IP 검증 솔루션
- 담당자 메모
- Cadence 사의 AVIP(Accelerated VIP)는 Cadence Palladium 및 Protium과 통합되어 하드웨어 기반 검증 환경에서 고속 시뮬레이션 성능을 제공하는 합성 가능한 Verification IP입니다.
Testbench와 DUT 간 데이터 전달을 가속화하며, 다양한 표준 프로토콜과 호환되어 대규모 SoC 검증의 병목을 해소합니다.
Features
- Compliance with PCIe and AMBA, Ethernet with support of critical erratas
- Verifies Root Complex, EndPoint, PHY, and Switch designs for all native widths and downgraded widths
- Comprehensive protocol checks with 3,300+ built-in checks/assertions
- Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation
- Static and dynamic setting for configuration variables available
- Root Complex, End Point, Switch, PHY DUT, Redriver 지원 가능
- Serial (NRZ, PAM4) and PIPE 6.2 (Serdes Architecture and Original Architecture)
- Supports all PCIe speeds: 2.5GT/s, 5.0GT/s, 8.0GT/s, 16GT/s, 32.0GT/s, 64GT/s
- FullVision 3.0 – new and improved high-performance debug engine
- Configurable link width support x1, x2, x4, x8, x12, x16
- Full support for up and down configuration
- Verifies Root Complex, EndPoint, PHY, and Switch designs for all native widths and downgraded widths
- Comprehensive protocol checks with 3,300+ built-in checks/assertions
- Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation
- Static and dynamic setting for configuration variables available
- Root Complex, End Point, Switch, PHY DUT, Redriver 지원 가능
- Serial (NRZ, PAM4) and PIPE 6.2 (Serdes Architecture and Original Architecture)
- Supports all PCIe speeds: 2.5GT/s, 5.0GT/s, 8.0GT/s, 16GT/s, 32.0GT/s, 64GT/s
- FullVision 3.0 – new and improved high-performance debug engine
- Configurable link width support x1, x2, x4, x8, x12, x16
- Full support for up and down configuration
